Present day ultra-large-scale integration (ULSI) circuits may include millions of interconnected active electronic devices fabricated on a silicon substrate and operating at clock rates of 1 Ghz or more. A substantial amount of time and money is needed to design, fabricate, and test such integrated circuits. Electronic design automation (EDA) tools are used in the design phase of integrated circuits to simulate the functional behavior of integrated circuits prior to their fabrication. These tools are used to confirm that an integrated circuit will function properly prior to its fabrication.
EDA tools are becoming more sophisticated in estimating design parameters such as signal transmission delay and power dissipation. Accurate signal delay estimation now generally requires a stronger link between front-end EDA tools which synthesize a design into a netlist of cells (active devices) and back-end EDA tools which place and route the cells of the synthesis. Without such a link, deep-submicron designs of integrated circuits may have to undergo multiple design iterations to meet design specifications. This process can be expensive and time consuming. The number of layout iterations needed to optimize a design generally increases significantly as logic density and clock speed of the integrated circuit increases. A more accurate signal delay estimation during front-end design generally leads to fewer time-consuming layout iterations.
As the minimum feature sizes of integrated circuits continue to shrink and operating speeds increase, the effects on signal delay due to the resistive, capacitive, and inductive parasitics of nets (e.g., wiring) which interconnect the active devices of the integrated circuit become more critical and more difficult to characterize. Accordingly, a complete analysis of the functional behavior of modem integrated circuit designs typically must account for the resistive, capacitive and inductive effects on signal delay of the interconnect paths. In the past, these parasitic effects of interconnect nets could generally be disregarded when simulating the operation of an integrated circuit, because the active devices therein typically dominated the overall signal delay calculations while the delays associated with interconnect nets were typically considered negligible. However, as the minimum feature sizes of integrated circuits continue to shrink, the ratio of interconnect net delay to total delay has increased substantially. EDA tools that predict interconnect signal transmission delay or extract wiring parasitics for back annotation into the circuit typically use distributed RC equivalent networks to model the interconnects.
FIG. 1 illustrates the steps for designing an integrated circuit). FIG. 1 shows subsequent design steps A, B, and C. As further discussed below, design step A includes design synthesis 110 performed by a synthesis tool. Design step B includes design placement 120 performed by a placement tool. Design step C includes design routing 130 performed by a routing tool.
Synthesis 110 transforms an abstract behavior description of an integrated circuit into a functionally equivalent structural description (i.e., a netlist of cells and wiring interconnect). The behavior description is represented in design database A. The netlist is represented in design database B. The components or cells from which the netlist is built are selected from a library. This library contains information necessary to perform embedded timing analysis on the netlist in design database B. More particularly, the library contains timing models for each of the cells therein. A timing model is a mathematical model of input-to-output delay of a path between an input pin and an output pin of the cell. Such a path is also called a timing arc. The library also contains a parasitic estimation model. The purpose of embedded timing analysis is to enable optimization within 110 until the integrated circuit meets the desired timing specification. The desired timing specification is represented by timing constraints and exceptions from the designer.
Design step A produces a slack distribution 118 which is a representation of the result of embedded timing analysis. Slack is the difference between required signal arrival time and actual signal arrival time at a measurement point in the integrated circuit. A slack distribution histogram displays the number of points for which the slack has a given value within a given resolution. For example, if the X-axis of the histogram displays time with the resolution of one nanoseconds (“ns”) and the Y-axis of the histogram displays the value 300 for the time value 7, then 300 points in the integrated circuit have a slack of 7 ns+/−0.5 ns.
Design step B specifies a physical location for each cell of the integrated circuit on a silicon substrate, printed circuit board, etc., based on the netlist in design database B. The result of design step B is represented in design database C. Placement performs embedded timing analysis and optimization. The timing models for arcs used in step B are similar to those used for design step A. However, the parasitic estimation model used in placement timing analysis and optimization is different than that used in step A. In design step A, parasitic estimation was based on structural circuit description only, whereas in design step B placement information is available for more accurate parasitic estimation. Slack distribution B 128, again provides a representation of the result of embedded timing analysis.
Design step C specifies physical interconnect routes between the individual cells based on the structural integrated circuit information and placement information in design database C. The result of design step C is represented in reference design database 140. Routing also performs embedded timing analysis and optimization. The timing model for arcs used in step C is similar to that used in design steps A and B. However, the parasitic estimation model used in placement timing analysis and optimization of step C is different than that used in steps A and B. The estimation model used in step C is more accurate than that used in design steps A and B because specific route information is available. Slack distribution 138 is generated and provides a representation of the result of embedded timing analysis. Slack distribution 138 again provides a representation of the result of embedded timing analysis for step C.
Reference timing analysis 142 is performed on design database 140 after step C to verify that the integrated circuit design meets the desired timing specification, based on. Reference timing analysis 142 performs embedded timing analysis and optimization. Timing models used in reference timing analysis 142 are similar to those used in design steps A, B, and C. However, the parasitic estimation model is different. Specific route information is available in reference design database 140 for all interconnections of the integrated circuit, whereas in design step C, only partial route information was available, as the routes were being specified. Therefore, the most accurate parasitic estimation model, also called parasitic extraction model, is chosen for timing analysis 142. Slack distribution 148 is generated to provide a representation of the result of embedded timing analysis.
FIG. 2 illustrates relevant details on timing analysis used in the steps shown in FIG. 1. Design database 210 (which corresponds to databases A, B, C or reference design database 140) contains information about the implementation of the integrated circuit. Depending on the available implementation information, an appropriate parasitic estimation model 295 is chosen. The parasitic estimation engine 220 calculates parasitic data 270 based on design database 210 and parasitic estimation model 295. The accuracy of the resulting parasitic data 270 depends on the available implementation information contained in database 210 and on the accuracy of the parasitic estimation model 295. The accuracy of the resulting parasitic data 270 depends also on the parasitic estimation engine 220.
Delay calculation engine 280 calculates timing data 290. This timing data calculation is based on design database 210, parasitic data 270, and timing model for arc 260. The accuracy of the resulting timing data 290 is limited by the accuracy of the parasitic data 270.
Timing analysis engine 230 combines timing data 290 along each path as defined by the structure of the integrated circuit given in design database 210. Timing analysis engine 230 compares the results of combining timing data 290 along each path against timing constraints and exceptions 250 to check whether the desired timing on the paths are met. The result is represented in slack distribution 240.
Timing closure is the agreement between timing results in design steps A, B, and C and the result of timing analysis 142. More particularly, timing closure is meet when the slack distributions resulting from embedded timing analyses in design steps A, B, and C, correlates with the slack distribution resulting from reference timing analysis.
The following conditions are necessary, but not sufficient, to achieve timing closure: similarity between the timing models for arc 260 used in steps A, B, and C; similarity between the delay calculation engines 280 used in steps A, B, and C; similarity between the timing analysis engines 230 used in steps A, B, and C, and; compatibility between timing constraints and exceptions 250 used in steps A, B, and. These conditions can be satisfied by choosing and qualifying appropriate EDA tools used in steps A, B, C and the reference timing analysis. For example: Design step A can be performed by the Design Compiler tool from Synopsys or by the BuildGates tool from Cadence; design step B can be performed by the Qplace tool from Cadence; and design step C can be performed by the Wroute tool from Cadence or by the Apollo tool from Avant!. Alternatively, a combination of design step A and design step B can be performed by the Physical Compiler tool from Synopsys, or the PKS tool from Cadence, etc.
Estimating the parasitics for each wire is one of the problems which arise during attempts to achieve timing closure in the design of an integrated circuit. In the front end of the design phase the placement, the length of each wire is not known. As such, the actual parasitic effects on signal delay cannot be accurately predicted at the front end of the design phase. A lumped resistance, capacitance, and inductance (RCL) is estimated for each wire at the front end of the design phase. Using a lumped RCL allows a designer to attempt to match the total distributed RCL on a wire which results in the back end of the design phase. But even if the estimated lumped RLC at the front end matches total RLC at the back end, the timing would not match, since the effect of distribution of the lumped RLC is neglected in the front end. Another problem is the lack of one-to-one correspondence of logical and physical wires. A logical wire may be broken into multiple physical wires by inserting buffers.
In theory, different timing engines analyzing a design under equivalent constraints should give matching results. However, for the following reasons the results must be verified for each design. Convergent timing arcs on a path may be handled algorithmically different by different engines. Timing exceptions (i.e. exclusion of non-relevant paths from analysis) may be handled differently by different engines, or the user may have made mistakes in specifying the intentionally equivalent timing exceptions in different tool-specific languages. This problem would be solved by using the same timing engine for each design step, but this is often not possible. A unique timing engine is embedded in each design tool. The unique timing engines cannot be exchanged between design tools. (As an analogy, a motor is an integral part of a car and cannot be arbitrarily replaced by a motor designed for a different car.)
Attempts in the related art to drive the EDA tools towards a common timing target by correlating the different factors of influence (e.g., electrical parasitics, timing characterization models, and timing engines) in isolation. In some instances, even with a large number of iterations, the timing correlation cannot be satisfied. As a consequence, the synthesis tool, the placement tool and the routing tool may anticipate a different timing result than the actually achieved timing result. Under design leads to excessive iterations, increasing the cost and delaying the production of the design. In the case of over design, the lack of timing correlation leads to a circuit which is larger, slower or consumes more power than necessary to accomplish the desired function.